Memory Architecture and Cell Design Employing Two Access Transistors

ABSTRACT

An improved memory array architecture and cell design is disclosed in which the cell employs two access transistors. In one embodiment, the two access transistors in each cell are coupled at one of their channel terminals to a memory element, which in turn is connected to a bit line. The other of the channel terminals are effectively tied together via reference lines. The word lines (i.e., gates) of the two access transistors are also tied together. The result in a preferred embodiment is a cell having two access transistors wired and accessed in parallel. With such a configuration, the widths of the access transistors can be made one-half the width of more-traditional one-access-transistor designs, saving layout space in that (first) dimension. Moreover, because the word lines of adjacent cells will be deselected, the improved design does not require cell-to-cell isolation (e.g., trench isolation) in the other (second) dimension. The result, when applied to a phase change memory, comprises about a 37% reduction in layout area from previous cell designs.

FIELD OF THE INVENTION

Embodiments of the invention relate to an improved memory arrayarchitecture and cell design employing two access transistors which isparticularly (but not exclusively) useful in the design of a phasechange memory.

BACKGROUND

Semiconductor memory integrated circuits are in high demand, and theindustry is always striving to improve the density of such devices.Currently, the Dynamic Random Access Memory (DRAM) is in widespread use.However, DRAM cells require a capacitor, which requires refreshing topreserve the stored data.

Accordingly, newer memory cell technologies are under consideration forthe mass market. One such new memory technology is the Phase ChangeRandom Access Memory (PCRAM). In a PCRAM, the capacitor of the DRAM cellis replaced with a phase change material, such asGermanium-Antimony-Telluride (GST) or other chalcogenide materials. Anexample of such a cell 30 as fabricated is shown in cross section inFIG. 1B, and is shown in schematic form in FIG. 1A. Because thestructure and operation of PCRAMs are well known to those skilled in theart, they are only briefly described. The a PCRAM cell is an excitingalternative to traditional capacitor-based DRAM cells because they donot require refresh and are easily scalable. (Capacitors require a givensurface area to store the requisite number of charges, and hence are noteasily scaled).

As shown, each PCRAM cell 30 comprises an access transistor 32 and aphase change material 34. Each access transistor 32 is selectable via aword line (row) 20, which when accessed opens a transistor channelbetween a bit line (column) 24 and a reference line 22. The phase changematerial 34 is in series between the transistor channel and the cellselection line 24, and so can be set (i.e., programmed), reset, or readvia the passage of current through the material. As is well known, phasechange material 34 can be set by passing a current therethrough, whichmodifies the material into a more conductive crystalline state. Thisphase change of the material 34 is reversible, and so the material 34may be reset back to an amorphous resistive state by the passage of evena larger amount of current through the material. Such phase changingoccurs in the region 34 a adjacent to the bottom electrode 42 b as shownin FIG. 1B. Once set or reset to make the material 34 relativelyconductive (denoting storage of a logic ‘1’) or resistive (denotingstorage of a logic ‘0’), the cell may be read by passing a relativelysmall current through the phase change material 34 and sensing theresulting voltage on the bit lines 24.

Processing of the PCRAM cell 30 uses standard semiconductor CMOSprocessing techniques, and does not require significant explanation tothose of skill in the art. As shown in FIG. 1B, the cell 30 usespolysilicon gate for the word lines 20 as is common, and uses conductiveplugs to contact the diffusion regions 44 in active portions of thesilicon substrate. The phase change material 34 is sandwiched betweentop and bottom electrodes 42 a and 42 b. Contact from the bit line 24 totop electrodes 42 a is established by plugs 40. Of course, conductivestructures are surrounded by at least one dielectric material 35, suchas silicon dioxide or silicon nitride as is well known. Pairs ofadjacent cells 30 are isolated from one another using trench isolation46, again a standard technique for isolating active structure in asilicon substrate.

Other details concerning PCRAM memory composition, operation, andfabrication can be found in the following references, all of which areincorporated by reference herein in their entireties: S. H. Lee et al.,“Full Integration and Cell Characteristics for 64 Mb Nonvolatile PRAM,”2004 Symp. on VLSI Technology Digest of Technical Papers, pps. 20-21(2004); S. Hudgens and B. Johnson, “Overview of Phase-ChangeChalcogenide Nonvolatile Memory Technology,” MRS Bulletin, pps. 829-832(November 2004); F. Yeung et al., “Ge₂Sb₂Te₅ Confined Structures andIntegration of 64 Mb Phase-Change Random Access Memory,” JapaneseJournal of Applied Physics, Vol. 44, No. 4B, pps. 2691-2695 (2005); Y.N. Hwang et al., “Full Integration and Reliability Evaluation ofPhase-change RAM Based on 0.24 um-CMOS Technologies,” 2003 Symposium onVLSI Technology Digest of Technical Papers, pps. 173-147 (2003); W. Y.Cho, et al., “A 0.18-um 3.0-V 64-Mb Nonvolatile Phase-Transition RandomAccess Memory (PRAM),” IEEE Journal of Solid-State Circuits, Vol. 40,No. 1, pps. 293-300 (January 2005); and F. Bedeschi, et al., “An 8 MbDemonstrator for High-Density 1.8V Phase-Change Memories,” 2004Symposium on VLSI Circuits Digest of Technical Papers, pps. 442-445(2004).

The layout of the PCRAM cells 30 in a memory array 10 is shown in a topview in FIG. 1C. The area corresponding to each cell 30 is generallydemarked with a dotted-lined oval. As can be seen each reference line 22is shared between a pair of cells 30 which also share the same bit line24. Each of these pairs of cells 30 are contained within the same activesilicon area, as shown by dotted lined box in FIG. 1C, which comprisesthe diffusion regions 44 and channel regions for the access transistors32 each of the cells in the pair. Outside of these active regions, thesilicon substrate comprises trench isolation 46 (see FIG. 1B), whichisolates adjacent cells from one another. The minimum width ‘x’ ofisolation required is dictated by layout design rules and can vary.

Laid out in this fashion, the array 10 of PCRAM cells 30 can be operatedas follows. First, a cell 30 to be accessed is determined by the logicof the integrated circuitry in which the array is formed (not shown),and an appropriate word line 20 and bit line 24 are respectivelyactivated via row decoder/driver circuitry 12 and column decoder/drivercircuitry 14. The reference drivers 16 send a reference potential toeach of the cells 30 in the array 10 at all times, which can be groundfor example. An activated word line 20 can comprise a voltage sufficientto form a channel under the access transistors, e.g., 1.5V. The voltageto be placed on the selected bit line 24 depends on whether the accessedcell is being set or reset (collectively, “programmed”), or read. Whenthe cell is being set, the voltage on the bit line might beapproximately 2.0V, and when reset a higher voltage of perhaps 3.0V canbe used. When the cell is being read, a smaller bit line 24 voltage isused (e.g., 0.5V), and the current draw through the bit line is assessedvia sense amplifiers (not shown) in the column decoder/driver circuitry14. Because such decoder/driver circuitry 12, 14, 16 is well known, itis not further discussed.

It has been discovered that the architecture of array 10 is not optimaland takes up too much space. Specifically, the layout of each cell 30 inthe array of FIG. 1C has been estimated to encompass an area equivalentto 16F², where F is the minimum lithography limit of the process used tofabricate the array 10. This is a relatively large area for a memorycell. In part, the relatively large size of the PCRAM cell is dictatedby the relatively high currents (e.g., on the order of milliamps) usedto set and reset the cells. Such large set and reset currents requiredaccess transistors 32 which are relatively wide, i.e., in which theactive diffusion areas 44 of the silicon are ‘y’ wide as shown in FIG.1C. Moreover, such large currents generally also require that the widthof the trench isolation 46 between the cells also be relatively large(i.e., ‘x’) so as to prevent cross-talk between the cells. While suchfactors may naturally warrant cells designs for PCRAMs which arerelatively large, the fact remains that there is room for improvement onthis score. Indeed, this disclosure presents a cell design and arrayarchitecture for a PCRAM and other memories that allows for a denserarray of cells.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the inventive aspects of this disclosure will be bestunderstood with reference to the following detailed description, whenread in conjunction with the accompanying drawings, in which:

FIGS. 1A, 1B, and IC illustrate a prior art design for a PCRAM memoryarray, and respectively show the array in schematic, cross sectional,and layout views.

FIGS. 2A, 2B, and 2C illustrate a design for a PCRAM or other memoryarray in accordance with an embodiment of the invention, andrespectively show the array in schematic, cross sectional, and layoutviews.

FIG. 3 illustrates an alternative design to that shown in FIGS. 2A-2C inwhich the reference lines are parallel with the bit lines in the array.

FIG. 4 illustrates an embodiment of the invention applied in the contextof a DRAM memory.

DETAILED DESCRIPTION

An improved memory array architecture and cell design is disclosed inwhich the cell employs two access transistors. The array architectureand cell design is particularly useful when employed in the content of aphase change memory, although they may be used in other contexts aswell, such as in more-traditional ROM and RAM designs. In oneembodiment, and to summarize one embodiment of the invention briefly,the two access transistors in each cell are coupled at one of theirchannel terminals to a memory element, which in turn is connected to abit line. The other of the channel terminals are effectively tiedtogether via reference lines. (Note: the bit lines and reference linesare reversible). Moreover, in one embodiment, the word lines providing agate voltage to the gates of the two access transistors are tiedtogether. The result in a preferred embodiment is a cell having twoaccess transistors wired and accessed in parallel. With such aconfiguration, the widths of the access transistors can be made one-halfthe width of more-traditional one-access-transistor designs whilepreserving current handling capacity. This saves layout space in that(first) dimension. Moreover, because the word lines of adjacent cellswill be deselected, the improved design does not require cell-to-celldielectric isolation (e.g., trench isolation) in the other (second)dimension. The result, when applied to a phase change memory, is a celldesign taking up a layout area of only approximately 10F², or about a37% reduction in layout area from the cell design of the prior art.

An embodiment of the improved PCRAM cell design and array architectureis shown in FIGS. 2A-2C, which basically corresponds to the same viewsof FIGS. 1A-1C as discussed in the Background. To the extent structuresin the improved design are not changed from the prior art designdiscussed in the background, they bear the same element numerals.

The first feature to be noticed in the new design is the cell 130. Asshown, each cell 130 comprises two access transistors 132 a, 132 b. In apreferred embodiment, the word lines 120 for each of the accesstransistors in a cell 130 (i.e., word lines 120 c and 120 d for accesstransistors 132 a and 132 b) are tied together, for example, within ornear the row decoder/driver circuitry 112, as exemplified by the dottedlines 117. When this is accomplished, the two access transistors 132 aand 132 b in each cell are simultaneously accessed.

Each of the access transistors 132 in each cell 130 are coupled togetherat a channel terminal to the lower electrode 42 b of the phase changematerial 34, which all share a common diffusion region 44 in thesubstrate. The other side (i.e., terminal) of the phase change materialis in turn coupled via its upper electrode 42 a to its bit line 24 aswas the case with the prior art (see FIG. 2B). The other channelterminals of the access transistors are coupled to different referenceslines 22 (e.g., 22 b and 22 c), and hence to different diffusion regions44. However, because each of the reference lines 22 are preferably tiedvia reference drivers 16 to a common potential (e.g., ground), theresulting circuit for each cell 130 in the improved array 100 is asillustrated to the lower left in FIG. 2A. To summarize, in the improvedcell design of FIG. 2A, two access transistors 132 a, 132 b areeffectively wired together in parallel.

At first blush, it would appear that the improved cell design 130 is notoptimal, as it requires the use of two access transistors 132 ascompared to a single access transistor 32 in the prior art. Conventionwisdom would therefore suggest that the new cell design 130 would belarger than the old cell design 130. However, as shown in the layoutperspective of FIG. 2C, this is not the case. As shown in FIG. 2C, thelocation of each two-transistor cell 130 is roughly bounded by thedotted-lined oval. When FIGS. 1C and 2C are compared, it is noticed thatthe cell density of the new cell design 130 is higher than that of theold cell design 30, despite the fact that the new cell design comprisestwo access transistors 132. In fact, estimations show that the new celldesign 130 encompasses an area of approximately only 10F². Thus, whencompared with the old design 30 of 16F², the new cell 130 results takeup an area that is approximately 37% smaller.

There are two main reasons for the improved cell density in the newdesign. First, because two access transistors 132 are available to carrythe cell's current, the access transistors can be half of the width(‘½y’) of the single access transistor 32 of the prior art (‘y’).Accordingly, the bit lines 24 in the array 100 can be placed ‘½y’ closertogether.

Second, the improved cell architecture makes it unnecessary to usetrench isolation 46 in the dimension perpendicular to the rows/wordlines 120. This is perhaps best illustrated in FIG. 2B. As discussedearlier, access to cell 130 would involve the simultaneous selection ofword lines 120 d and 120 c, e.g., by placing a voltage of 1.5V on thosegates. However, this would mean that all other word lines 120 areinactive, e.g., grounded, such as adjacent gates 120 e and 120 b in FIG.2B. Because no channel will form under these deselected gates,activation of cell 130 will not disturb adjacent cells. In effect, thedeselected transistors gates 120 e and 120 b function similarly to thetrench isolation 46 of the prior art cell 30/array 10 (see FIG. 1B).Accordingly, while the improved cell 130 is naturally longer in thisdimension because of the use of two access transistors 132, thatincrease is offset by reductions afforded by disposing of the trenchisolation 46 in this dimension.

To summarize, the disclosed embodiment of an improved cell 130/array 100for a PCRAM achieves a smaller density than had otherwise been disclosedin the prior art. Moreover, such improved design requires almost nochanges to the decoder/driver circuitry used to bias the array, the onlysignificant change being splitting the signal for the selected rowbetween two word lines 120 (see row decoder/driver 112 of FIG. 2A).

In the embodiment of FIG. 2, note that the reference lines 22 runparallel with the word lines 120 and perpendicular to the bit lines 24.However, as shown in the alternative schematic of FIG. 3, thisorientation of the reference lines 24 can changed such that they areperpendicular to the word lines 120 and parallel to the bit lines 24.Given the layout and fabrication details already disclosed, one skilledin the art would easily understand how to make such an alternative, andhence superfluous cross-sectional and layout views of this alternativeare not shown.

Although disclosed in the context of an improved cell design/arrayarchitecture for a PCRAM, it should be understood that embodiments ofthe invention are not so limited. For example, the cell design/arrayarchitecture can be used with other types of memory elements aside fromphase change materials 34. In one simple example, the phase changematerial 34 in each cell could be modified to comprise a one-timeprogrammable fuse or antifuse, allowing for the formation of aProgrammable Read Only Memory (PROM). Moreover, the disclosed techniquescan be applied to the fabrication of other memory technologies, such asRRAMs (Resistance Random Access Memories), and MRAMs (Magnetic RandomAccess Memory), which may also need relatively large programmingcurrents. In short, while the disclosed embodiment is particularlyuseful in the context of a PCRAM, it is not so limited and indeed mayapply to other memory elements (e.g., fuses, antifuses, etc.) as well.

Indeed, the disclosed cell design/array architecture can be used withDRAMs as well, as shown in FIG. 4. As shown, storage capacitors 150 havetaken the place of the phase change material 34. Additionally, ascompared to the schematic of FIG. 3, noticed that the reference driver16 and column decoder/driver circuit 14 are exchanged. This exchangeallows the reference drivers 16 to place a suitable reference potentialon the reference plate of the storage capacitors 150 via reference lines24, such as ½Vdd as is typical in DRAM technologies. When the cell isaccessed, both transistors 132 in the DRAM cell are selected as inearlier embodiments, with the result that the storage plate of thestorage capacitor 150 is now coupled through both transistors 132 to itsassociated bit line 122, where it can be written to or read via thecolumn decoder/driver circuitry 14. In short, the disclosedtwo-access-transistor/one-memory-element cell is applicable totraditional RAM technologies, as well as ROM, PROM, or erasable PROMtechnologies.

Other modifications are possible. For example, although this disclosurehas contemplated that both of the access transistors 132 be accessed inparallel (i.e., by essentially tying their word lines 120 c, 102 dtogether at the row decoder/driver 112 via 117), this need not alwaysoccur in other useful embodiments of a two-access-transistor cell. Ifthe word lines 120 c and 120 d are decoupled as is more normal for amemory array, then each access transistor 132 in each cell 130 can beindependently accessed. This can have advantages. For example, during aset operation, high currents are not needed through the accesstransistors and so only one (e.g., 132 a) need to be activated. Bycontrast, during a higher-current reset operation, both accesstransistors 132 a, 132 b could be activated. A reading operation couldlikewise include activating one or both of the access transistors ineach cell. Of course, such an embodiment would require modifications tothe row decoder/driver circuitry, but such modifications are minor andeasily achievable by those of skill in the art.

Additionally, it is not important to some embodiments of the inventionwhich lines in the array act as sensing (bit) lines or reference linesas these are reversible. Moreover, although it has been disclosed thatdifferent operational conditions such as read, set, and reset areimplementable by using different bit line voltages, it should beunderstood that different access transistor 132 gate voltages could beused as well. For example, during any of these operating conditions, thevoltage on the bit lines 24 can be held constant, with the gate voltageof the access transistors 132 being increased to achieve an appropriateamount of drive current for the condition at hand. Thus, a high gatevoltage can be used for setting, and a higher gate voltage forresetting. Such multiple gate voltages would ultimately requiredifferent voltages on the word lines 120, which in turn would requiremodifications to the row decoder/driver circuits 112. But tailoring suchvoltages is well within the skill on those skilled in the art, and henceis not further discussed. Moreover, the reference lines can also beseparately addressed and biased as well to provide additionalflexibility in other circuit designs.

While a preferred embodiment of the invention has been disclosed, itshould be understood the circuitry as disclosed herein can be modifiedwhile still achieving the various advantages discussed herein. In short,it should be understood that the inventive concepts disclosed herein arecapable of many modifications. To the extent such modifications fallwithin the scope of the appended claims and their equivalents, they areintended to be covered by this patent.

1. A memory cell for an integrated circuit, comprising: a memory elementfor storing a logic state; and two access transistors coupled to thememory element, wherein the two access transistors are coupled inparallel and are simultaneously accessed to couple to the memoryelement.
 2. The memory cell of claim 1, wherein the two accesstransistors each comprise a gate, a first channel terminal, and a secondchannel terminal, and wherein the access transistors are coupledtogether and simultaneously accessed by tying the gates together, tyingthe first channel terminals together, and tying the second channelterminals together.
 3. The memory cell of claim 2, wherein the memoryelement comprises a first terminal and a second terminal, and whereinthe two access transistors are coupled to the first terminal of thememory element.
 4. The memory cell of claim 2, wherein the first channelterminals of the access transistors are tied together by sharing acommon diffusion region in a substrate.
 5. The memory cell of claim 4,wherein the second channel terminals of the access transistors do notshare a common diffusion region in the substrate.
 6. The memory cell ofclaim 3, wherein the second terminal of the memory element is coupled toeither a bit line or a reference potential.
 7. The memory cell of claim6, wherein the second channel terminals of the access transistors arecoupled to the other of the bit line or the reference potential.
 8. Thememory cell of claim 1, wherein the memory element comprises a phasechange material.
 9. The memory cell of claim 1, wherein the memoryelement comprises a fuse or antifuse.
 10. The memory cell of claim 1,wherein the memory element comprises a capacitor.
 11. The memory cell ofclaim 1, wherein the memory element comprises a RRAM memory element or aMRAM memory element.
 12. A memory cell for an integrated circuit,comprising: a memory element for storing a logic state, the memoryelement having a first terminal and a second terminal; a first accesstransistor having first and second channel terminals, wherein a firstchannel terminal of the first transistor is coupled to the firstterminal of the memory element; and a second access transistors havingfirst and second channel terminals, wherein a first channel terminal ofthe second transistor is coupled to the first terminal of the memoryelement.
 13. The memory cell of claim 12, wherein first and secondaccess transistors each comprise a gate, and wherein the gates are tiedtogether.
 14. The memory cell of claim 12, wherein the first channelterminals of the first and second access transistors and the firstterminal of the memory element are tied together by sharing a commondiffusion region in a substrate.
 15. The memory cell of claim 12,wherein the second channel terminals of the access transistors do notshare a common diffusion region in the substrate.
 16. The memory cell ofclaim 12, wherein the second channel terminals are tied together. 17.The memory cell of claim 12, wherein the second terminal of the memoryelement is coupled to either a reference potential or a bit line, andwherein the second channel terminals of the access transistors arecoupled to the other of the reference potential or the bit line.
 18. Thememory cell of claim 12, wherein the memory element comprises a phasechange material.
 19. The memory cell of claim 12, wherein the memoryelement comprises a fuse or antifuse.
 20. The memory cell of claim 12,wherein the memory element comprises a capacitor.
 21. The memory cell ofclaim 12, wherein the memory element comprises a RRAM memory element ora MRAM memory element.
 22. A memory cell for an integrated circuit,comprising: a material capable of holding a logic state; and two accesstransistors coupled to the material each for accessing the logic stateof the material.
 23. The memory cell of claim 22, where in the materialcomprises a phase change material.
 24. The memory cell of claim 23,wherein the material comprises GST.
 25. The memory cell of claim 22,wherein the two access transistors are coupled together in parallel. 26.The memory cell of claim 22, wherein the memory cell further comprises aword line coupled to gates of the access transistors, and a bit linecoupled to the material.
 27. The memory cell of claim 22, wherein theaccess transistors share only one common diffusion region in asubstrate.
 28. The memory cell of claim 22, wherein the accesstransistors are independently selectable by two word lines.
 29. A memoryarray for an integrated circuit comprising a plurality of memory cells,comprising: a plurality of word lines parallel to a first dimension, aplurality of bit lines parallel to a second dimension perpendicular tothe first dimension; a plurality of reference lines; and a plurality ofmemory cells, wherein each cell comprises: a memory element with a firstterminal and a second terminal; and two access transistors selectable bytwo of the word lines, the two access transistors having first andsecond channel terminals, wherein the first channel terminals of the twoaccess transistors are coupled to the first terminal of the memoryelement.
 30. The memory array of claim 29, wherein the second terminalof the memory element is coupled to one of the bit lines, and whereineach second channel terminals of the access transistors is coupled toits own one of the reference lines.
 31. The memory array of claim 29,wherein the second terminal of the memory element is coupled to one ofthe bit lines, and wherein both the second channel terminals of theaccess transistors are coupled to one reference line.
 32. The memoryarray of claim 29, wherein the second terminal of the memory element iscoupled to one of the reference lines, and wherein both the secondchannel terminals of the access transistors are coupled to one bit line.33. The memory array of claim 29, wherein the reference lines areparallel to the first dimension.
 34. The memory array of claim 29,wherein the reference lines are parallel to the second dimension. 35.The memory array of claim 29, wherein the two word lines for selectingthe two access transistors are coupled together.
 36. The memory array ofclaim 29, wherein the two word lines for selecting the two accesstransistors are independently controllable.
 37. The memory array ofclaim 29, wherein the cells do not comprise cell-to-cell dielectricisolation in the first dimension.
 38. The memory array of claim 29,wherein the two access transistors are coupled together in parallel andselectable in parallel.
 39. The memory array of claim 29, wherein thememory element comprises a phase change material.
 40. The memory arrayof claim 29, wherein the memory element comprises a fuse, an antifuse, acapacitor, a RRAM memory element, or a MRAM memory element.
 41. A memoryarray for an integrated circuit comprising a plurality of memory cells,comprising: a plurality of word lines parallel to a first dimension, aplurality of bit lines parallel to a second dimension perpendicular tothe first dimension; a plurality of reference lines; and a plurality ofmemory cells, wherein each cell comprises: a memory element for storinga logic state; and two access transistors coupled to the memory element,where the two access transistors are selectable by two of the wordlines, and wherein the two access transistors are coupled in paralleland are simultaneously accessed to couple to the memory element.
 42. Thememory array of claim 41, wherein the second terminal of the memoryelement is coupled to one of the bit lines, and wherein each secondchannel terminals of the access transistors is coupled to its own one ofthe reference lines.
 43. The memory array of claim 41, wherein thesecond terminal of the memory element is coupled to one of the bitlines, and wherein both the second channel terminals of the accesstransistors are coupled to one reference line.
 44. The memory array ofclaim 41, wherein the second terminal of the memory element is coupledto one of the reference lines, and wherein both the second channelterminals of the access transistors are coupled to one bit line.
 45. Thememory array of claim 41, wherein the reference lines are parallel tothe first dimension.
 46. The memory array of claim 41, wherein thereference lines are parallel to the second dimension.
 47. The memoryarray of claim 41, wherein the two word lines for selecting the twoaccess transistors are coupled together.
 48. The memory array of claim41, wherein the two word lines for selecting the two access transistorsare independently controllable.
 49. The memory array of claim 41,wherein the cells do not comprise cell-to-cell dielectric isolation inthe first dimension.
 50. The memory array of claim 41, wherein the twoaccess transistors are coupled together in parallel and selectable inparallel.
 51. The memory array of claim 41, wherein the memory elementcomprises a phase change material.
 52. The memory array of claim 41,wherein the memory element comprises a fuse, an antifuse, a capacitor, aRRAM memory element, or a MRAM memory element.
 53. A method foroperating a memory cell, comprising: activating first and second accesstransistors simultaneously during a first operational mode of the memorycell, and activating only one of the first and second access transistorsduring a second operational mode of the memory cell, wherein the cellcomprises a memory element for storing a logic state, the memory elementhaving a first terminal and a second terminal, and wherein the firstaccess transistor is coupled to the first terminal of the memoryelement, and wherein the second access transistors is coupled to thefirst terminal of the memory element.
 54. The method of claim 53,wherein the first operational mode is resetting the memory element, andwherein the second operational mode is setting the memory element. 55.The method of claim 54, wherein the memory element is a phase changematerial.
 56. The method of claim 53, wherein first and second accesstransistors each comprise a gate, and wherein activating the first andsecond transistors simultaneously comprises tying the gates together.57. The method of claim 53, wherein the first and second accesstransistors are coupled to the first terminal of the memory element bysharing a common diffusion region in a substrate.
 58. The method ofclaim 53, wherein the second terminal of the memory element is coupledto either a reference potential or a bit line.
 59. A method foroperating a memory cell, comprising: activating gates of first andsecond access transistors simultaneously during a first operational modeof the memory cell using a first gate voltage, and activating the gatesof the first and second access transistors simultaneously during asecond operational mode of the memory cell using a second gate voltagesmaller than the first gate voltage, and wherein the cell comprises amemory element for storing a logic state, the memory element having afirst terminal and a second terminal, and wherein the first accesstransistor is coupled to the first terminal of the memory element, andwherein the second access transistors is coupled to the first terminalof the memory element.
 60. The method of claim 59, wherein the firstoperational mode is resetting the memory element, and wherein the secondoperational mode is setting the memory element.
 61. The method of claim59, wherein the memory element is a phase change material.
 62. Themethod of claim 59, wherein activating the first and second transistorssimultaneously comprises tying the gates together.
 63. The method ofclaim 59, wherein the first and second access transistors are coupled tothe first terminal of the memory element by sharing a common diffusionregion in a substrate.
 64. The method of claim 59, wherein the secondterminal of the memory element is coupled to either a referencepotential or a bit line.